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ADSP-21371 / ADSP-21375
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f VCO specified in Table 14 .
? The product of CLKIN and PLLM must never exceed 1/2
f VCO (max) in Table 14 if the input divider is not enabled
(INDIV = 0).
? The product of CLKIN and PLLM must never exceed f VCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
f INPUT = CLKIN when the input divider is disabled or
f INPUT = CLKIN ? 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12 . All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to t PCLK . See the peripheral specific section
for each peripheral’s timing information.
Table 12. Clock Periods
Timing
The VCO frequency is calculated as follows:
f VCO = 2 × PLLM × f INPUT
f CCLK = (2 × PLLM × f INPUT ) ? (2 × PLLD )
where:
Requirements
t CK
t CCLK
t PCLK
Description
CLKIN Clock Period
Processor Core Clock Period
Peripheral Clock Period = 2 × t CCLK
f VCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hard-
ware Reference .
f INPUT = Input frequency to the PLL.
PMCTL
(SDCKR)
PMCTL
PLL
(PLLBP)
XTAL
CLKIN
BUF
CLKIN
DIVIDER
f INPUT
LOOP
FILTER
VCO
f VCO
PLL
DIVIDER
PMCTL
(2xPLLD)
f CCLK
CCLK
SDRAM
DIVIDER
SDCLK
PMCTL
(INDIV)
PLL
MULTIPLIER
PMCTL
(PLLBP)
DIVIDE
BY 2
PCLK
PCLK
CLK_CFGx/PMCTL (2xPLLM)
CCLK
CLKOUT ( TEST ONLY)
RESET
DELAY OF
4096 CLKIN
RESETOUT
BUF
RESETOUT
CYCLES
CORERST
Figure 4. Core Clock and System Clock Relationship to CLKIN
Rev. D | Page 19 of 56 | April 2013
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